This invention relates to CMOS integrated circuits, and particularly to the fabrication of N-type and P-type field effect transistors (NFETs and PFETs) for improved device performance.
It is known that mechanical stress can affect the performance of semiconductor devices. Specifically, stress affects the mobility of carriers in semiconductors. Individual stress tensor components may cause different effects on the device behavior of PFETs and NFETs respectively. A uniaxial tensile stress, longitudinally applied (that is, in the same direction as the channel current), enhances performance of an NFET but degrades the performance of a PFET. A longitudinally applied compressive stress reverses the effect; it enhances performance of a PFET but degrades that of an NFET. However, a transversely applied uniaxial tensile stress (normal to the direction of the channel current) enhances performance of both NFETs and PFETs simultaneously.
A biaxial stress will improve the NFET to a greater degree than a uniaxial stress, but will not improve the PFET because the two stress components have effects that cancel in the PFET. Previous workers have found that when an in-plane biaxial tensile stress is applied, NFET device performance improves about twofold compared to performance under uniaxial tensile stress, while PFET performance is unchanged.
In order to maximize the performance of both NFET and PFET devices through the application of mechanical stress, the stress components should be applied differently for the two types of devices. Previous attempts to use mechanical stress for device performance enhancement have not improved both NFETs and PFETs simultaneously. order to increase the speed of CMOS circuits, there is a need for a method for providing tension in both the longitudinal and transverse directions (with respect to channel current) for the NFET, while at the same time providing compression in the longitudinal direction and tension in the transverse direction for the PFET.
The present invention addresses the above-described need by providing a method of increasing the speed of CMOS circuits by imposing different longitudinal stresses on NFET and PFET devices. In accordance with the present invention, this is done by forming localized extended defects in the semiconductor material to introduce a longitudinal tensile stress for the NFETs while at the same time applying a longitudinal compressive stress for the PFETs.
A feature of the invention is the creation of voids/bubbles in sources and drains of NFETs to impose tensile stress in the body of the NFETs and the creation of dislocation loops or precipitates in sources and drains of PFETs to impose compressive stress in the body of PFETs.
Another feature of the invention is the implantation of elements from the fourth and sixth column of the periodic table in PFETs.
Another feature of the invention is the implantation of noble gases from the eighth column of the periodic table (and hydrogen) in NFETS.
A noteworthy advantage of the present invention is that performance of both NFET and PFET devices is improved simultaneously. It will also be appreciated that the process of the invention may readily be integrated into circuit fabrication processes known in the art. In addition, the present invention may be practiced in the fabrication of structures on bulk, SOI or strained Si substrates, and in both logic and memory devices. Furthermore, the present invention offers the advantage of significant device performance improvement at low cost.